1. Technical Field of the Invention
The present invention concerns the area of voltage generation circuits, in particular voltage regulators (for example, those included in integrated circuits in the form of an electronic chip).
2. Description of Related Art
Some chips have analog blocks and digital blocks supplied by respective different voltages, e.g. 2.5 V for analog blocks and 1.2 V for digital blocks.
In such cases, it is therefore possible to use part of the voltage supply for the analog blocks to supply a digital or analog block, making it possible for example to eliminate the need to have recourse to a switching power supply.
For this purpose, voltage generators are used, in the present case regulators, which must be capable of meeting consumption peaks corresponding to demands for current from digital blocks when these come into operation.
A conventional regulator R is illustrated FIG. 1a. The regulator R comprises an amplifier with a feedback loop, and an output power PMOS transistor (Pout) which supplies an external capacitor (Cext) acting as load ballast towards the digital or analog load (DL).
When the digital or analog block is in operation, this implies peak current consumption on the output line (Vout). If the peak is low, the current is supplied by the external capacitor (Cext), and if the peak is high or lasts a certain time, the external capacitor discharges and the loop 1 allows action from the output (Vout) on the amplifier input so as to lower the gate of the power transistor (Pout) to restore current.
However, said circuit is relatively slow, and incompatible with current response time needs, which are in the order of a few nanoseconds.
Additionally, load quantity can raise a problem. For example, whereas the standby current on the output line (Vout) may be 1 mA, the current demanded by a load may be 100 mA. A circuit such as shown FIG. 1a cannot meet said demand, since it is not fast enough. Said circuits are not adapted for pulse responses, i.e. their output voltage (Vout) may drop further to demand for current from the digital or analog block.
To overcome these disadvantages, reference is made to French Application for Patent No. 2881236 (the disclosure of which is hereby incorporated by reference). FIG. 1b illustrates a circuit for the production of reference voltages to supply an analog/digital converter.
In this configuration, the output is looped back to the input of the amplifier, so that the output (Vout) is servo-controlled by the reference voltage (Vref) in the form of a slow loop as mentioned above. The reference FR 2881236 also proposes a fast loop 1′, at an output stage of the amplifier.
In FIG. 1b, the output stage is magnified and shown in dashed lines. The gate of the PMOS transistor M2 is fixed by the slow loop, and allows a low impedance node to be obtained.
When the digital or analog block makes a demand for current, the source of the PMOS transistor M2 decreases, and the transistor cuts off. Yet, since the current source I0 is constant (as is current source I1), more current circulates through the NMOS transistor M3 (whose gate is at a fixed voltage VB) acting on the gate of the PMOS power transistor M1, whose gate voltage decreases rapidly, allowing current to be supplied to the digital or analog block.
The group of transistors M1, M2 and M3 defines the fast loop 1′, which can provide very fast response times, typically in the order of a few nanoseconds, between the load current demand (IL) and the response of the power transistor M1.
It is true that the above-described circuit is adapted for the supply of an analog/digital converter, whose consumption magnitude is in the order of a factor of 20 to 50 (a few dozen microamperes), yet it is not optimal for use with a regulator whose consumption is in the order of factor one thousand.
Additionally, the load of the digital or analog block is not always known.
There is a need to overcome these drawbacks.